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TMS570LS3137 Scheda tecnica(PDF) 81 Page - Texas Instruments |
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TMS570LS3137 Scheda tecnica(HTML) 81 Page - Texas Instruments |
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81 / 173 page ![]() TMS570LS3137 www.ti.com SPNS162C – APRIL 2012 – REVISED APRIL 2015 The parity protection for peripheral RAMs is not enabled by default and must be enabled by the application. Each individual peripheral contains control registers to enable the parity protection for accesses to its RAM. NOTE The CPU read access gets the actual data from the peripheral. The application can choose to generate an interrupt whenever a peripheral RAM parity error is detected. Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications 81 Submit Documentation Feedback |
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