TNETE2004

MDIO-MANAGED QuadPHY

FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

29

POST OFFICE BOX 655303

mode 2 receive-data timing

MIN

TYP

MAX

UNIT

tRDLAT

Receive-data latency

500

ns

tPD

Receive data

40

60

ns

tCRSHO

Time from receiver idle to carrier sense off

200

ns

RCVP/

RCVN

RXCLK

(see Note B)

CRS

tRDLAT

tCRSHO

tPD

RXD

(see Note A)

NOTES: A. During a collision, the data output on RXD is not valid received data (or looped-back transmit data) since the digital PLL is acquiring

lock to a different source of incoming data.

B. RXCLK goes high seven clock cycles after CRS goes high.

Figure 19. Mode 2 Receive Timing