PCM1802 datasheet(13/24 Pages) TI

13 / 24 page

PCM1802

SLES023B – DECEMBER 2001 – REVISED MARCH 2002

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PRINCIPLES OF OPERATION

system clock

The PCM1802 supports 256 fS, 384 fS, 512 fS, and 768 fS as the system clock, where fS is the audio sampling

frequency. The system clock must be supplied on SCKI (pin 15).

The PCM1802 has a system clock detection circuit which automatically senses if the system clock is operating

at 256 fS, 384 fS, 512 fS, or 768 fS in slave mode. In master mode, the system clock frequency must be selected

by MODE0 (pin 19) and MODE1 (pin 20), and 768 fS is not available. For system clock inputs of 384 fS, 512 fS,

and 768 fS, the system clock is divided to 256 fS automatically, and the 256 fS clock is used to operate the

delta-sigma modulator and the digital filter.

Table 1 shows the relationship of typical sampling frequencies and system clock frequencies, and Figure 22

shows system clock timing.

Table 1. Sampling Frequency and System Clock Frequency

SAMPLING RATE

FREQUENCY

SYSTEM CLOCK FREQUENCY (MHz)

FREQUENCY

(kHz)

256 fS

384 fS

512 fS

768 fS

8.192

12.288

16.384

24.576

44.1

11.2896

16.9344

22.5792

33.8688

12.288

18.432

24.576

36.864

16.384

24.576

32.768

49.152

88.2

22.5792

33.8688

45.1584

—

24.576

36.864

49.152

—

SCKI

0.8 V

SCKI

2.0 V

tSCKL

tSCKH

PARAMETER

MIN

MAX

UNIT

tSCKH

System clock pulse width, high

tSCKL

System clock pulse width, low

Figure 22. System Clock Timing

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