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CY2280
Document #: 38-07207 Rev. *A
Page 3 of 12
Function Table (-11S Option)
SEL100
SEL1
SEL0
SEL_SS[2]
CPU/PCI
Ratio
CPUCLK
PCICLK_F
PCICLK
REF
APIC
USBCLK
0
0
0
N/A
2
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
0
1
N/A
2
Reserved
Reserved
14.318 MHz
14.318 MHz
48 MHz
0
1
0
N/A
2
Reserved
Reserved
14.318 MHz
14.318 MHz
48 MHz
0
1
1
0 (downspread)
2
66.66 MHz 33.33 MHz
14.318 MHz
14.318 MHz
48 MHz
0
1
1
1 (no spread)
2
66.66 MHz 33.33 MHz
14.318 MHz
14.318 MHz
48 MHz
1
0
0
N/A
3
TCLK/2
TCLK/6
TCLK[3]
TCLK[3]
TCLK/2
1
0
1
N/A
3
Reserved
Reserved
14.318 MHz
14.318 MHz
48 MHz
1
1
0
N/A
3
Reserved
Reserved
14.318 MHz
14.318 MHz
48 MHz
1
1
1
0 (downspread)
3
100 MHz
33.33 MHz
14.318 MHz
14.318 MHz
48 MHz
1
1
1
1 (no spread)
3
100 MHz
33.33 MHz
14.318 MHz
14.318 MHz
48 MHz
Function Table (-21S Option)
SEL100
SEL1
SEL0
SEL_SS[2]
CPU/PCI
Ratio
CPUCLK
PCICLK_F
PCICLK
REF
APIC
USBCLK
0
0
0
N/A
2
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
0
1
N/A
2
Reserved
Reserved
14.318 MHz
Reserved
48 MHz
0
1
0
N/A
2
Reserved
Reserved
14.318 MHz
Reserved
48 MHz
0
1
1
0 (downspread)
2
66.66 MHz 33.33 MHz
14.318 MHz
16.67 MHz
48 MHz
0
1
1
1 (no spread)
2
66.66 MHz 33.33 MHz
14.318 MHz
16.67 MHz
48 MHz
1
0
0
N/A
3
TCLK/2
TCLK/6
TCLK[3]
TCLK/12[3]
TCLK/2
1
0
1
N/A
3
Reserved
Reserved
14.318 MHz
Reserved
48 MHz
1
1
0
N/A
3
Reserved
Reserved
14.318 MHz
Reserved
48 MHz
1
1
1
0 (downspread)
3
100 MHz
33.33 MHz
14.318 MHz
16.67 MHz
48 MHz
1
1
1
1 (no spread)
3
100 MHz
33.33 MHz
14.318 MHz
16.67 MHz
48 MHz
Actual Clock Frequency Values
Clock Output
Target Frequency
(MHz)
Actual Frequency
(MHz)
PPM
CPUCLK
66.67
66.654
–195
CPUCLK
100
99.77
–2346
USBCLK
48.0
48.008
167
Power Management Logic
CPU_STOP
PCI_STOP
PWR_DWN
CPUCLK
PCICLK
PCICLK_F
Other
Clocks
Osc.
PLLs
X
X
0
Low
Low
Low
Low
Off
Off
0
0
1
Low
Low
Running
Running
Running Running
0
1
1
Low
Running
Running
Running
Running Running
1
0
1
Running
Low
Running
Running
Running Running
1
1
1
Running
Running
Running
Running
Running Running
Notes:
2.
Target frequency is modulated by percentage shown (max.) when SEL_SS = 0.
3.
TCLK supplied on the XTALIN pin in Test Mode.
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