2 / 7 page
CY29940
Document #: 38-07283 Rev. *B
Page 2 of 7
Note:
1.
PD = Internal Pull-Down, PU = Internal Pull-up.
Pin Description[1]
Pin
Name
PWR
I/O
Description
5
PECL_CLK
I, PU
PECL Input Clock
6
PECL_CLK#
I, PD
PECL Input Clock
3TCLK
I, PD
External Reference/Test Clock Input
9, 10, 11, 13,
14, 15, 18, 19,
20, 22, 23, 24,
26, 27, 28, 30,
31, 32
Q(17:0)
VDDC
O
Clock Outputs
4
TCLK_SEL
I, PD
Clock Select Input. When LOW, PECL clock is selected and when
HIGH TCLK is selected.
8, 16, 29
VDDC
3.3V or 2.5V Power Supply for Output Clock Buffers
7, 21
VDD
3.3V or 2.5V Power Supply
1, 2, 12, 17,
25
VSS
Common Ground
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