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PCM1793DBR Scheda tecnica(PDF) 16 Page - Texas Instruments |
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PCM1793DBR Scheda tecnica(HTML) 16 Page - Texas Instruments |
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16 / 25 page ![]() PCM1793 SLES076A − MARCH 2003 − REVISED JANUARY 2004 www.ti.com 16 DATA t(BCH) 1.4 V BCK LRCK t(BCL) t(LB) t(BCY) t(DS) t(DH) 1.4 V 1.4 V t(BL) PARAMETERS MIN MAX UNITS t(BCY) BCK pulse cycle time 70 ns t(BCL) BCK pulse duration, LOW 30 ns t(BCH) BCK pulse duration, HIGH 30 ns t(BL) BCK rising edge to LRCK edge 10 ns t(LB) LRCK edge to BCK rising edge 10 ns t(DS) DATA setup time 10 ns t(DH) DATA hold time 10 ns — LRCK clock duty 50% ± 2 bit clocks Figure 25. Timing of Audio Interface |
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