PIFE32251B-R68MS datasheet(146/157 Pages) TI1

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TPS650830

SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016

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Layout

9.1.3

Layout Checklist

•

All inductors, input/output caps and FETs for the converters and controller should be on the same

board layer as the IC.

•

Place feedback connection points near the output capacitors and minimize the control feedback loop

as much as possible to achieve the best regulation performance.

•

Bootstrap capacitors must be place close to the IC from the SWVRx to VBSTVRx pins.

•

DRVLVRx signals must be routed on the same layer as the IC and the FETs and minimize the length

and parasitic inductance of the trace as much as possible.

•

Each converter and controller should have their own separate ground and each ground should connect

to the common ground separately. The input capacitors, output capacitors, and FET grounds for each

VRx converter and controller must be connected to the ground plane for the respective VRx rail. Since,

the PGNDs for each rail are not connect to each other or AGND, it is required to use the PGNDVRx

pins for the input and output capacitors for each VRx rail. This ground plane should connect in one

place to the common ground close to the input and output capacitor ground pads. See the figure below

for a visual representation of the converter layout scheme.

•

The internal reference regulators must have their input and output caps close to the IC pins.

•

Route the FBVRxP and FBVRxN signals as a differential pair.

9.2

Layout Example

9.2.1

Controller Layout

The routing of the controllers is critical to the performance of the power supply. To reduce the risk of the

controller effecting other sensitive circuits on the board, it is recommended to place all of the controller

components on the same layer are the PMIC. In addition to component placement, the DRV, SW, and

PGND signals should be routed on the same layer or as few of layers possible. It is recommended to

place the FETs as close as possible to the PMIC but, it is imperative that the input capacitors are placed

with minimal distance from the VIN and PGND pads of the FETs. The feedback signals should be routed

differentially to the furthest output capacitor, which should be placed close to the load. Be sure to not route

the feedback or any analog sensitive signals under the inductor, next to the SW node, or between the CIN

and the FETs due to the high frequency switching from the edges.

If the FETs of the controller are to be place far away from the PMIC the layout of the DRV, SW and PGND

signals becomes extremely critical. The loop inductance of the the traces must be minimized as much as

possible. In-order to do this, pair the DRVH and SW traces together and pair the DRVL and PGND traces

together. PGND is best routed as a plane. To reduce the loop inductance of the DRVL, DRVL trace should

be routed one layer above the PGND. Generally, the SW, DRVL and DRVH traces should be 20 mils or

larger assuming the PGND is a plane underneath the DRVL trace.

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