PIFE32251B-R68MS datasheet(132/157 Pages) TI1

132 / 157 page

Converter

SWVR2

FBVR2P

FBVR2N

VINVR2

PGVRx

ENVRx

VREGVRx

1 PF

LDO5V

Cin

3.3V

Vout

Cout

Lout

100

4%5 (*5) =

nl4&5KJ × l+1%.+:8+0F8176;× 8176

2 × . × B59 × 8+0

3200À

F8µ#r×20GÀ

+64+2

132

TPS650830

SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016

www.ti.com

Submit Documentation Feedback

Product Folder Links: TPS650830

Application and Implementation

If the controller has high side current limit then, use Equation 5 to calculate the high side RCS resistor. The

high side current limit must be set higher than the low side current limit. Again, since the current limit is

when the inductor current is near its maximum it is recommended to use the saturation derating of the

inductor when calculating the RCS.

(5)

7.2.2.1.6 Selecting the Input Capacitors

Because of the nature of the switching converter and controller with a pulsating input current, a low ESR

input capacitor is required for best input voltage filtering and minimizing the interference with other circuits

caused by high input voltage spikes. For the controller, 12 µF of input capacitance is recommended for

most applications. To achieve the low ESR requirement, a ceramic capacitor is recommended. However,

the voltage rating and DC bias characteristic of ceramic capacitors need to be considered. The input

capacitor can be increased without any limit for better input voltage filtering. Be sure to size the ceramic

capacitor to achieve the recommended input capacitance. A ceramic capacitor placed as close as possible

to the respective VINx and PGNDx pins of the FETs is recommended.

The preferred capacitors for the controllers are two muRata GRM21BR61E106MA73: 10 μF, 0805, 25 V,

±20% or similar.

7.2.2.2

Converter Design Procedure

Designing the converter has only 2 steps: designing the output filter and selecting the input capacitors.

The converter must be supplied by a 3.3-V source which can be provided by one of the TPS65083x

controllers.

The converter requires VREG supply and capacitors. VREG should be connected to the 5-V LDO and a 1-

µF, X5R, 20%, 10-V or similar capacitor should be used for decoupling.

Figure 7-4. Converter Diagram

PIFE32251B-R68MS Scheda tecnica(PDF) 132 Page - Texas Instruments

PIFE32251B-R68MS Scheda tecnica(HTML) 132 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL