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DS3134 Scheda tecnica(PDF) 5 Page - Dallas Semiconductor

Il numero della parte DS3134
Spiegazioni elettronici  Chateau Channelized T1 And E1 And HDLC Controller
PDF  203 Pages
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Produttore elettronici  DALLAS [Dallas Semiconductor]
Homepage  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS3134 Scheda tecnica(HTML) 5 Page - Dallas Semiconductor

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DS3134
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TABLE OF CONTENTS
Section 1: Introduction……………………………………………………………………………………..7
Section 2: Signal Description…………………………………………………………………………… 16
2.1 Overview / Signal Lead List………………………………………………………………… 16
2.2 Serial Port Interface Signal Description……………………………………………………
22
2.3 Local Bus Signal Description………………………………………………………………. 24
2.4 JTAG Signal Description…………………………………………………………………… 27
2.5 PCI Bus Signal Description………………………………………………………………… 28
2.6 Supply & Test Signal Description…………………...…………………………………….. 31
Section 3: Memory Map………………………………………………………………………………… 32
3.0 Introduction………………………………………………………………………………….. 32
3.1 General Configuration Registers…………………………………………………………..
32
3.2 Receive Port Registers……………………………………………………………………..
33
3.3 Transmit Port Registers……………………………………………………………………. 33
3.4 Channelized Port Registers………………………………………………………………..
34
3.5 HDLC Registers……………………………………………………………………………. 35
3.6 BERT Registers…………………………………………………………………………….. 35
3.7 Receive DMA Registers……………………………………………………………………. 35
3.8 Transmit DMA Registers…………………………………………………………………… 36
3.9 FIFO Registers……………………………………………………………………………… 36
3.10 PCI Configuration Registers for Function 0…………………………………………….
36
3.11 PCI Configuration Registers for Function 1…………………………………………….
37
Section 4: General Device Configuration & Status/Interrupt………………………………………….. 37
4.1 Master Reset & ID Register Description………………………………………………….
37
4.2 Master Configuration Register Description……………………………………………….
38
4.3 Status & Interrupt…………………………………………………………………………… 40
4.3.1 Status & Interrupt General Description………………………………………
40
4.3.2 Status & Interrupt Register Description………………………………………
43
4.4 Test Register Description…………………………………………………………………..
50
Section 5: Layer One…………………………………………………………………………………… 51
5.1 General Description………………………………………………………………………… 51
5.2 Port Register Description…………………………………………………………………..
55
5.3 Layer One Configuration Register Description…………………………………………..
59
5.4 Receive V.54 Detector……………………………………………………………………..
65
5.5 BERT…………………………………………………………………………………………69
5.6 BERT Register Description………………………………………………………………..
70
Section 6: HDLC………………………………………………………………………………………… 77
6.1 General Description………………………………………………………………………..
77
6.2 HDLC Register Description……………………………………………………………….
79



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