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AP0100CS Scheda tecnica(PDF) 19 Page - ON Semiconductor |
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AP0100CS Scheda tecnica(HTML) 19 Page - ON Semiconductor |
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19 / 73 page ![]() AP0100CS/D Rev. 6, Pub. 1/16 EN 19 ©Semiconductor Components Industries, LLC,2016. AP0100CS HDR: Image Signal Processor (ISP) Image Flow Processor Image Flow Processor Image and color processing in the AP0100CS is implemented as an image flow processor (IFP) coded in hardware logic. During normal operation, the embedded microcontroller will automatically adjust the operating parameters. For normal operation of the AP0100CS, streams of raw image data from the attached image sensor are fed into the color pipeline. The user also has the option to select a number of test patterns to be input instead of sensor data. The IFP is broken down into different sections, as outlined in Figure 12. Figure 12: AP0100CS IFP linear or com panded data D efect cor r ection , N oise r eduction RX decom panding Black level subtr action , D igital gain contr ol, PG A RA W 12- or 20-b it B a ye r AE, F D and ALT M stats 1 2 -b it AL T M Ba ye r Color Inter polation ALT M Color Cor r ection Aper tur e C or r ection Gam m a RG B 2YU V AW B stats Color Kill YU V filter s Scaler Cr op Progressive T est pattern generator ST E Inter lacer Over lay RA W B a ye r AL T M Ba ye r RG B YC b C r PAL /N T SC Test patter ns PAL /N T SC Encode D AC Progres s iv e (Y CbCr or Bay er) C C IR656 (Y CbCr) NT S C /PAL (Y CbCr) |
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