AS4C2M32SA datasheet(17/54 Pages) ALSC

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SelfRefresh Exit command

This command is used to exit from the SelfRefresh mode. Once this command is registered, NOP or

Device Deselect commands must be issued for tXSR(min.) because time is required for the completion

of any bank currently being internally refreshed. If auto refresh cycles in bursts are performed during

normal operation, a burst of 4096 auto refresh cycles should be completed just prior to entering and just

after exiting the SelfRefresh mode.

Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L")

When the SDRAM is operating the burst cycle, the internal CLK is suspended (masked) from the

subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held intact

while CLK is suspended. On the other hand, when all banks are in the idle state, this command

performs entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are

turned off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown

state longer than the refresh period (64ms) since the command does not perform any refresh

operations.

Clock Suspend Mode Exit / PowerDown Mode Exit command (CKE= "H")

When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from the

subsequent cycle by providing this command (asserting CKE "HIGH", the command should be NOP or

deselect). When the device is in the PowerDown mode, the device exits this mode and all disabled

buffers are turned on to the active state. tPDE (min.) is required when the device exits from the

PowerDown mode. Any subsequent commands can be issued after one clock cycle from the end of this

command.

Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H")

During a write cycle, the DQM signal functions as a Data Mask and can control every word of the

input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is also used

for device selection, byte selection and bus control in a memory system.

AS4C2M32SA-6TIN

AS4C2M32SA-6TCN

AS4C2M32SA-7TCN

Confidential

-17/54-

Rev.1.0 Sep. 2015

AS4C2M32SA Scheda tecnica(PDF) 17 Page - Alliance Semiconductor Corporation