CS9211 datasheet(11/62 Pages) NSC

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Signal Definitions (Continued)

FLM

(8 mA)

Offset

404h[24] = 0

First Line Marker (SSTN/DSTN Panels)

This is the frame pulse for the flat panel data indicating a

display frame is about to start.

Depending on the type of panel being interfaced, this signal

can alsobereferred toasFPorFRAME.

VSYNC

Offset

404h[24] = 1

Vertical Sync (TFT Panels)

VSYNC is the vertical sync for active-matrix TFT panel. This

is a delayed version of the input VSYNC signal with the

appropriate pipeline delay relative to the pixel data on

UD[11:0] and LD[11:0].

If pin 33 is selected as VSYNC at Offset 404h[24], its polar-

ity is programmable through Offset 404h[23]:

0= Active high; 1 = Active low.

DISPOFF#

(8 mA)

---

Disables Backlight

When this output is asserted low, it turns the backlight off.

FP_VDDEN

(8 mA)

---

Controls LCD VDD FET

When this output is asserted high, VDD voltage is applied

to the panel. This signal is intended to control a power FET

to the LCD panel. The FET may be internal to the panel or

not, depending on the panel manufacturer

FP_VCONEN

(8 mA)

---

Controls LCD Bias Voltage Enable

When this output is asserted high, the contrast voltage is

applied to the panel. This signal should be connected

directly to the panel.

2.2.3

Flat Panel Interface Signals (Continued)

Signal Name

Pin No.

Type

(Drive)

Function

Selection

Description

2.2.4

Memory Interface Signals

Signal Name

Pin No.

Type

(Drive)

Description

MA[10:0]

135, 132,

134, 137,

139, 140,

141, 142,

143, 138,

136

(8 mA)

Memory Address Bus

These signals are the address bits to the external frame buffer. Ten bits are

used for EDO (Extended Data Out) DRAM and eleven bits are used for

SDRAM.

Row and column addresses are multiplexed on the same pins.

MD[15:0]

102, 104,

106, 110,

112, 114,

116, 118,

119, 117,

115, 113,

111, 107,

105, 103

I/O

(8 mA)

Memory Data Bus

These bidirectional signals are the external frame buffer data bus.

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