ASM3P2182A

http://onsemi.com

2

Figure 1. Block Diagram

ModOUT

PLL

CLKIN

Crystal

Oscillator

VSS

S0

FS0 FS1

VCO

Output

Divider

Loop

Filter

Phase

Detector

Modulation

Frequency

Divider

Feedback

Divider

Table 1. PIN DESCRIPTION

Pin #

Pin Name

Type

Description

1

CLKIN

I

Connect to externally generated clock signal.

2

GND

P

Ground to entire chip.

3

S1

I

Spread range select. Digital logic input used to select frequency deviation

(Refer to Spread Deviation Table). This pin has an internal pull−up resistor.

4

S0

I

Spread range select. Digital logic input used to select frequency deviation

(Refer to Spread Deviation Table). This pin has an internal pull−up resistor.

5

ModOUT

O

Spread spectrum low EMI output.

6

VDD

P

Power supply for the entire chip (3.3 V).

7

FS0

I

Frequency range select. Digital logic input used to select frequency range

(Refer to Input Frequency and Modulation Rate Table).

This pin has an internal pull−up resistor.

8

FS1

I

Frequency range select. Digital logic input used to select frequency range

(Refer to Input Frequency and Modulation Rate Table).

This pin has an internal pull−up resistor.

Table 2. INPUT FREQUENCY AND MODULATION RATE TABLE

FS1 (pin 8)

FS0 (pin 7)

Frequency Range

0

0

25 MHz to 50 MHz

0

1

50 MHz to 103 MHz

1

0

75 MHz to 150 MHz

1

1

160 MHz to 210 MHz

Table 3. SPREAD DEVIATION SELECTION TABLE

S1

S0

Spreading Range (+%)

25 MHz

40 MHz

65 MHz

81 MHz

(Note 1)

81 MHz

(Note 2)

108 MHz

120 MHz

162 MHz

200 MHz

0

0

0.28

0.19

0.15

0.12

0.18

0.15

0.1

0.1

0.06

0

1

0.8

0.3

0.3

0.2

0.5

0.3

0.19

0.3

0.1

1

0

1.2

0.54

0.45

0.4

0.8

0.6

0.36

1.0

0.6

1

1

2.1

1.0

1.1

0.9

1.4

1.1

0.75

1.9

1.2

1. Frequency Range: 50 MHz to 103 MHz

2. Frequency Range: 75 MHz to 150 MHz