LM4817 datasheet(19/21 Pages) NSC

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Application Information (Continued)

Resistor value for V

UT and VLT are determined as follows:

(The application of Figure 6 used a G

T of 5µ mho)

The above procedure assumes a rail-to-rail output compara-

tor. Essentially, R

2 is in parallel with R1 prior to reaching the

lower threshold, then R

2 becomes parallel with R3 for the

upper threshold. Note that the application requires rail-to-rail

input as well.

The resistor values shown in Figure 7 are the closest prac-

tical to calculated values.

Fast Start-up

The LM4817’s LDO provides fast start-up time for better

system efficiency. The start-up speed is maintained when

using the optional noise bypass capacitor. An internal 500µA

current source charges the capacitor until it reaches about

90% of its final value.

RECOMMENDED PRINTED CIRCUIT BOARD LAYOUT

Figures 8 through 10 show the recommended two-layer PC

board layout that is optimized for the 28-pin MH-packaged

LM4817 and associated components. These circuits are

designed for use with an external 5V supply and 8

Ω (or

greater) speakers.

This circuit board is easy to use. Apply 5V and ground to the

board’s V

DD and GND pads, respectively. Connect speakers

between the board’s -OUTA and +OUTA and OUTB and

+OUTB pads. Apply the stereo input signal to the input pins

labeled "-INA" and "-INB." The stereo input signal’s ground

references are connected to the respective input channel’s

"GND" pin, adjacent to the input pins.

200781C0

FIGURE 7. Minimum Battery Detector that Disconnects

the Load Via the SHDN Pin of the LM4817

200781D2

FIGURE 8. Recommended MH board layout:

component-side silkscreen

20078145

FIGURE 9. Recommended MHPC board layout:

component-side layout

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