Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

Preview PDF HTML

QL4016 Scheda tecnica(PDF) 5 Page - List of Unclassifed Manufacturers

Il numero della parte QL4016
Spiegazioni elettronici  16,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM
PDF  18 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  ETC [List of Unclassifed Manufacturers]
Homepage  
Logo ETC - List of Unclassifed Manufacturers

QL4016 Scheda tecnica(HTML) 5 Page - List of Unclassifed Manufacturers

  QL4016 Datasheet HTML 1Page - List of Unclassifed Manufacturers QL4016 Datasheet HTML 2Page - List of Unclassifed Manufacturers QL4016 Datasheet HTML 3Page - List of Unclassifed Manufacturers QL4016 Datasheet HTML 4Page - List of Unclassifed Manufacturers QL4016 Datasheet HTML 5Page - List of Unclassifed Manufacturers QL4016 Datasheet HTML 6Page - List of Unclassifed Manufacturers QL4016 Datasheet HTML 7Page - List of Unclassifed Manufacturers QL4016 Datasheet HTML 8Page - List of Unclassifed Manufacturers QL4016 Datasheet HTML 9Page - List of Unclassifed Manufacturers Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 18 page
background image
© 2002 QuickLogic Corporation
www.quicklogic.com
5
•
•
•
•
•
•
QL4016 QuickRAM Data Sheet Rev I
Figure 4: QuickRAM Module
Table 2: RAM Cell Synchronous Write Timing
Symbol
Parameter
Propagation Delays (ns)
Fanout
1
2
3
4
5
t
SWA
WA Setup Time to WCLK
1.0
1.0
1.0
1.0
1.0
tHWA
WA Hold Time to WCLK
0.0
0.0
0.0
0.0
0.0
t
SWD
WD Setup Time to WCLK
1.0
1.0
1.0
1.0
1.0
t
HWD
WD Hold Time to WCLK
0.0
0.0
0.0
0.0
0.0
tSWE
WE Setup Time to WCLK
1.0
1.0
1.0
1.0
1.0
t
HWE
WE Hold Time to WCLK
0.0
0.0
0.0
0.0
0.0
t
WCRD
WCLK to RD (WA=RA)a
a. Stated timing for worst case Propagation Delay over process variation at V
CC = 3.3 V and
TA = 25
° C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature
settings as specified in the Operating Range.
5.0
5.3
5.6
5.9
7.1
Table 3: RAM Cell Synchronous Read Timing
Symbol
Parameter
Propagation Delays (ns)
Fanout
Logic Cells
1
2
3
4
5
tSRA
RA Setup Time to RCLK
1.0
1.0
1.0
1.0
1.0
t
HRA
RA Hold Time to RCLK
0.0
0.0
0.0
0.0
0.0
t
SRE
RE Setup Time to RCLK
1.0
1.0
1.0
1.0
1.0
tHRE
RE Hold Time to RCLK
0.0
0.0
0.0
0.0
0.0
t
RCRD
RCLK to RDa
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and
TA = 25
× C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature
settings as specified in the Operating Range.
4.0
4.3
4.6
4.9
6.1
WA
WD
WE
WCLK
RE
RCLK
RA
RD
[8:0]
[17:0]
[8:0]
[17:0]
MODE
ASYNCRD
[1:0]



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18


Scheda tecnica Scarica

Go To PDF Page


Link URL



Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   Collegamento alla scheda tecnica    |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com