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ADP7157ACPZ-04-R7 Scheda tecnica(PDF) 23 Page - Analog Devices |
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ADP7157ACPZ-04-R7 Scheda tecnica(HTML) 23 Page - Analog Devices |
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23 / 24 page ![]() ADP7157 Data Sheet Rev. A | Page 22 of 23 OUTLINE DIMENSIONS 2.48 2.38 2.23 0.50 0.40 0.30 10 1 6 5 0.30 0.25 0.20 PIN 1 INDEX AREA SEATING PLANE 0.80 0.75 0.70 1.74 1.64 1.49 0.20 REF 0.05 MAX 0.02 NOM 0.50 BSC EXPOSED PAD 3.10 3.00 SQ 2.90 PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY 0.08 TOP VIEW BOTTOM VIEW 0.20 MIN Figure 65. 10-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-10-9) Dimensions shown in millimeters COMPLIANT TO JEDEC STANDARDS MS-012-A A 1.27 0.40 1.75 1.35 2.29 2.29 0.356 0.457 4.00 3.90 3.80 6.20 6.00 5.80 5.00 4.90 4.80 0.10 MAX 0.05 NOM 3.81 REF 0.25 0.17 8° 0° 0.50 0.25 45° COPLANARITY 0.10 1.04 REF 8 1 4 5 1.27 BSC SEATING PLANE FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. BOTTOM VIEW TOP VIEW 0.51 0.31 1.65 1.25 Figure 66. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-1) Dimensions shown in millimeters |
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