ML610Q411 datasheet(2/36 Pages) LAPIS

2 / 36 page

FEDL610Q411-04

ML610Q411/ML610Q412

2/36

• Watchdog timer

− Non-maskable interrupt and reset

− Free running

− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)

• Timers

− 8 bits × 4 channels (Timer0-3: 16-bit x 2 configuration available by using Timer0-1 or Timer2-3)

− Clock frequency measurement mode (in one channel of 16-bit configuration using Timer2-3)

• 1 kHz timer

− 10 Hz/1 Hz interrupt function

• Capture

− Time base capture × 2 channels (4096 Hz to 32 Hz)

• PWM

− Resolution 16 bits × 1 channel

• Synchronous serial port

− Master/slave selectable

− LSB first/MSB first selectable

− 8-bit length/16-bit length selectable

• UART

− TXD/RXD × 1 channel

− Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits

− Positive logic/negative logic selectable

− Built-in baud rate generator

• I2C bus interface

− Master function only

− Standard mode (50kbps)

• Buzzer driver

− 4 output modes, 8 frequencies, 16 duty levels

• RC oscillation type A/D converter

− 24-bit counter

− Time division × 2 channels

• Successive approximation type A/D converter

− 12-bit A/D converter

− Input × 2 channels

− Conversion time: 46us/1ch@500kHz

• General-purpose ports

− Non-maskable interrupt input port × 1 channel

− Input-only port × 6 channels (including secondary functions)

− Output-only port × 3 channels (including secondary functions)

− Input/output port

ML610Q411: 22 channels (including secondary functions)

ML610Q412: 14 channels (including secondary functions)

• LCD driver

− The number of segments

ML610Q411: 144 dots max. (36 seg

× 4 com)

ML610Q412: 176 dots max. (44 seg

× 4 com)

− 1/1 to 1/4 duty

− 1/3 bias (built-in bias generation circuit)

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