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ML610Q438 Scheda tecnica(PDF) 5 Page - LAPIS Semiconductor Co., Ltd. |
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ML610Q438 Scheda tecnica(HTML) 5 Page - LAPIS Semiconductor Co., Ltd. |
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5 / 39 page ![]() FEDL610Q438-04 ML610Q438/ML610Q439 5/39 BLOCK DIAGRAM ML610Q438 Block Diagram Figure 1 show the block diagram of the ML610Q438. "*" indicates the secondary function of each port. Figure 1 ML610Q438 Block Diagram Program Memory (Flash) 128Kbyte SSIO SCK0* SIN0* SOUT0* UART RXD0* TXD0* I 2C SDA* SCL* INT 1 RAM 6144byte CPU (nX-U8/100) Timing Controller EA SP On-Chip ICE Instruction Decoder BUS Controller Instruction Register INT 1 INT 1 INT 3 PWM ×3 GPIO P00 to P03 P10 to P11 P20 to P22 INT 5 NMI P30 to P35 P40 to P47 Data-bus PWM0* to PWM2* Melody INT 1 MD0* TEST RESET_N OSC XT0 XT1 OSC0* OSC1* LSCLK* OUTCLK* BLD Power VDDL LCD Driver COM0 to COM23 SEG0 to SEG55 LCD BIAS VL1, VL2, VL3, VL4 C1, C2, C3, C4 RC-ADC ×2 CS0* IN0* RS0* RT0* CRT0* RCM* CS1* IN1* RS1* RT1* RESET & TEST ALU EPSW1~3 PSW ELR1~3 LR ECSR1~3 DSR/CSR PC GREG 0~15 VPP VDD VSS VDDX INT 1 Display RAM 192Byte Display Allocation RAM 1KByte Interrupt Controller TBC INT 4 INT 1 WDT INT 4 8bit Timer ×4 Capture ×2 1kHzTC INT 1 AVDD AVSS 12bit-ADC AIN0, AIN1 VREF INT 1 |
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