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ML7396AB Scheda tecnica(PDF) 26 Page - LAPIS Semiconductor Co., Ltd. |
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ML7396AB Scheda tecnica(HTML) 26 Page - LAPIS Semiconductor Co., Ltd. |
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26 / 140 page ![]() FEDL7396A/B/E-07 ML7396A/B/E 26/140 ■Functional Description ●SPI ML7396 family has a Serial Peripheral Interface (SPI), which supports slave mode. Host MCU can read/write to the ML7396 registers and on-chip FIF using MCU clock. Single access mode and burst access mode are also supported. [Single access mode] In write operation, data will be stored into internal register at rising edge of clock which is capturing D0 data. During write operation, if setting SCEN line to “H”, the data will not be sotred into register. SCEN SDI SCLK Write Data Field Address Field W SCEN SDI SCLK Address Field R SDO Read Data Field [Write] [Read] A 6 A 0 A 6 A 0 D 7 D 0 D 7 D 0 ”1” ”0” [Note] When using IEEE802.15.4d mode, it is need to read “Length+1” bytes of data from RX FIFO for switching the FIFO banks correctly. After reading Lngth bytes of data, need to access [RD_RX_FIFO:B0 0x7F] register once more. (The last byte is invalid data.) |
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