SN54ALS160B, SN54ALS162B, SN54AS160, SN54AS162

SN74ALS160B, SN74ALS162B, SN74AS160, SN74AS162

SYNCHRONOUS 4-BIT DECADE COUNTERS

SDAS024A – D2661, APRIL 1982 – REVISED MAY 1986

POST OFFICE BOX 655303

4

typical clear, preset, count, and inhibit sequences

0

Async

Clear

3

2

1

9

8

7

Preset

Sync

Clear

Outputs

Data

Inputs

RCO

QD

QC

QB

QA

ENT

ENP

CLK

D

C

B

A

LOAD

CLR

Inhibit

Count

’ALS160B, ’AS160, ’ALS162B, ’AS162

Illustrated below is the following sequence:

1. Clear outputs to zero (’ALS160B and ’AS160 are asynchronous; ’ALS162B and ’AS1162 are synchronous)

2. Preset to BCD seven

3. Count to eight, nine, zero, one, two, and three

4. Inhibit