ADPD2210

Data Sheet

Rev. A | Page 14 of 15

EVALUATION BOARD

Figure 27 shows the evaluation board schematic. Figure 28 and Figure 29 show the evaluation board layout for the top and bottom layers,

respectively.

Figure 27. Evaluation Board Schematic

Figure 28. Evaluation Board Layout, Top Layer

Figure 29. Evaluation Board Layout, Bottom Layer

GENERATE THE VOLTAGE OUTPUT.

ADPD2210

1

2

3

5

6

PWDN

OUT

GND

VCC

IN

REF

EPAD

V

P

O

G

R1D

DNI

R2D

100kΩ

C2D

1µF

C1D

0.01µF

D1D

4