LM1973 datasheet(7/11 Pages) NSC

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Application Information (Continued)

TABLE 1. LM1973 Micropot Attenuator

MSB:

LSB

Address Register (Byte 0)

0000 0000

Channel 1

0000 0001

Channel 2

0000 0010

Channel 3

Data Register (Byte 1)

Contents

Attenuation Level dB

0000 0000

0.0

0000 0001

0.5

0000 0010

1.0

0000 0011

1.5

:::::

0001 1110

15.0

0001 1111

15.5

0010 0000

16.0

0010 0001

17.0

0010 0010

18.0

:::::

0011 1110

46.0

0011 1111

47.0

0100 0000

48.0

0100 0001

50.0

0100 0010

52.0

:::::

0100 1100

72.0

0100 1101

74.0

0100 1110

76.0

0100 1111

100.0 (Mute)

0101 0000

100.0 (Mute)

:::::

1111 1110

100.0 (Mute)

1111 1111

100.0 (Mute)

µPot SYSTEM ARCHITECTURE

The µPot’s digital interface is essentially a shift register,

where serial data is shifted in, latched, and then decoded. As

new data is shifted into the DATA-IN pin, the previously

latched data is shifted out the DATA-OUT pin. Once the data

is shifted in, the LOAD/SHIFT line goes high, latching in the

new data. The data is then decoded and the appropriate

switch is activated to set the desired attenuation level for the

selected channel. This process is continued each and every

time an attenuation change is made. Each channel is up-

dated, only, when that channel is selected for an attenuator

change or the system is powered down and then back up

again. When the µPot is powered up, each channel is placed

into the muted mode.

µPot LADDER ARCHITECTURE

Each channel of a µPot has its own independent resistor lad-

der network. As shown in

Figure 8, the ladder consists of

multiple R1/R2 elements which make up the attenuation

scheme. Within each element there are tap switches that se-

lect the appropriate attenuation level corresponding to the

data bits in

Table 1. It can be seen in Figure 8 that the input

impedance for the channel is a constant value regardless of

which tap switch is selected, while the output impedance

varies according to the tap switch selected.

DIGITAL LINE COMPATIBILITY

The µPot’s digital interface section is compatible with either

TTL or CMOS logic due to the shift register inputs acting

upon a threshold voltage of 2 diode drops or approximately

1.4V.

DIGITAL DATA-OUT PIN

The DATA-OUT pin is available for daisy-chain system con-

figurations where multiple µPots will be used. The use of the

daisy-chain configuration allows the system designer to use

only one DATA and one LOAD/SHIFT line per chain, thus

simplifying PCB trace layouts.

In order to provide the highest level of channel separation

and isolate any of the signal lines from digital noise, the

DATA-OUT pin should be terminated througha2k

Ω resistor

if not used. The pin may be left floating, however, any signal

noise on that line may couple to adjacent lines creating

higher noise specs.

DS011958-9

FIGURE 7. Serial Data Format Transfer Process

DS011958-11

FIGURE 8. µPot Ladder Architecture

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