DS2155 datasheet(2/262 Pages) DALLAS

2 / 262 page

DS2156

2 of 262

TABLE OF CONTENTS

MAIN FEATURES........................................................................................................................................8

DETAILED DESCRIPTION......................................................................................................................11

2.1

BLOCK DIAGRAM...........................................................................................................................................13

FIGURE 2-1. BLOCK DIAGRAM................................................................................................................................13

FIGURE 2-2. RECEIVE AND TRANSMIT LIU (TDM BACKPLANE ENABLED)...........................................................14

FIGURE 2-3. RECEIVE AND TRANSMIT LIU (UTOPIA BACKPLANE ENABLED).....................................................15

FIGURE 2-4. RECEIVE AND TRANSMIT FRAMER/HDLC..........................................................................................16

FIGURE 2-5. BACKPLANE INTERFACE (TDM BACKPLANE ENABLED) ...................................................................17

FIGURE 2-6. BACKPLANE INTERFACE (UTOPIA BUS ENABLED)...........................................................................18

PIN FUNCTION DESCRIPTION .............................................................................................................19

3.1

TDM BACKPLANE .........................................................................................................................................19

3.1.1

Transmit Side ........................................................................................................................................19

3.1.2

Receive Side ..........................................................................................................................................22

3.2

UTOPIA BUS.................................................................................................................................................25

3.2.1

Receive Side ..........................................................................................................................................25

3.2.2

Transmit Side ........................................................................................................................................26

3.3

PARALLEL CONTROL PORT PINS ...................................................................................................................27

3.4

EXTENDED SYSTEM INFORMATION BUS........................................................................................................28

3.5

USER OUTPUT PORT PINS ..............................................................................................................................29

3.6

JTAG TEST ACCESS PORT PINS.....................................................................................................................30

3.7

LINE INTERFACE PINS....................................................................................................................................31

3.8

SUPPLY PINS ..................................................................................................................................................32

3.9

L AND G PACKAGE PINOUT...........................................................................................................................33

TABLE 3-A. PIN DESCRIPTION SORTED BY PIN NUMBER (TDM BACKPLANE ENABLED) .....................................33

TABLE 3-B. PIN DESCRIPTION SORTED BY PIN NUMBER (UTOPIA BACKPLANE ENABLED) ................................35

3.10

10MM CSBGA PIN CONFIGURATION ........................................................................................................37

FIGURE 3-1. 10MM CSBGA PIN CONFIGURATION (TDM SIGNALS SHOWN).........................................................37

PARALLEL PORT .....................................................................................................................................38

4.1

REGISTER MAP ..............................................................................................................................................38

TABLE 4-A. REGISTER MAP SORTED BY ADDRESS ................................................................................................38

4.2

UTOPIA BUS REGISTERS ..............................................................................................................................44

TABLE 4-B. UTOPIA REGISTER MAP.....................................................................................................................44

SPECIAL PER-CHANNEL REGISTER OPERATION.........................................................................45

PROGRAMMING MODEL.......................................................................................................................47

FIGURE 6-1. PROGRAMMING SEQUENCE.................................................................................................................47

6.1

POWER-UP SEQUENCE...................................................................................................................................48

6.1.1

Master Mode Register...........................................................................................................................48

6.2

INTERRUPT HANDLING ..................................................................................................................................49

6.3

STATUS REGISTERS........................................................................................................................................49

6.4

INFORMATION REGISTERS .............................................................................................................................50

6.5

INTERRUPT INFORMATION REGISTERS ..........................................................................................................50

CLOCK MAP ..............................................................................................................................................51

FIGURE 7-1. CLOCK MAP (TDM MODE).................................................................................................................51

T1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS..............................................52

8.1

T1 CONTROL REGISTERS ...............................................................................................................................52

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