MP7528JS datasheet(8/16 Pages) EXAR

8 / 16 page

MP7528

Rev. 2.00

INTERFACE LOGIC INFORMATION

DAC Selection: Both DAC latches share a common 8-bit in-

put port. The control input DACA/DACB selects which DAC can

accept data from the input port.

Mode Selection: Inputs CS and WR control the operating

mode of the selected DAC. See Mode Selection Table below:

Write Mode: When CS and WR are both low the selected

DAC is in the write mode. The input data latches of the selected

DAC are transparent and its analog output responds to activity

on DB0-DB7.

Hold Mode: The selected DAC latch retains the data which

was present on DB0-DB7 just prior to CS and WR assuming a

high state. Both analog outputs remain at the values corre-

sponding to the data in their respective latches.

Table 1. Mode Selection Table

DAC A

L = LOW state, H = HIGH state, X = Don’t care state

DAC A/DAC B

DAC B

Write

Hold

Write

Hold

Figure 1. Write Cycle Timing Diagram

tCS

tCH

tWR

tDS

tDH

DATA IN

STABLE

VIH

VIL

VIH

VIL

DATA IN

(DB0-DB7)

NOTES:

All input signal rise and fall times measured from 10% to 90% of VDD.

VDD = +5 V, tr = tf = 20 ns

VDD = +15 V, tr = tf = 40 ns

Timing measurement reference level is VIH + VIL / 2

tAS

tAH

DAC A/DAC B

VDD

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