GS7660

Vishay

formerly General Semiconductor

Document Number 74819

www.vishay.com

24-May-02

7

∑P loss =

P outp.

Res.

P switch

Res.

P cap.

Res.

+ P conversion

++

P outp.

Res.

2

f = f osc/2

P switch

Res.

+

2

P cap.

Res.

P conversion =

1

2

1

2

f

C2

C1

f = f osc /2

=

[

Voltage Doubling

Figure 11 shows two methods of voltage doubling. In Fig.

11a , R1 is added to ensure that doubling is not inhibited

by a non-destructive latch-up at start-up. This condition can

pin ( pin 8) during start-up.

R1 increases output impedance and in higher current

applications where the voltage drop across R1 exceeds a two

diode drop, the doubling circuit of Fig 11b is recommended.

The voltage doubler of Fig. 11a is more accurate at low

load currents since the voltage drop across the diode is not

reflected at the output.

Figs. 11a and 11b – Voltage Doubler

1

2

3

4

8

7

6

5

8

7

6

5

10

µF

R1

200

Ω

1N914

C1

C2

10

µF

+

+

(3.0V to 12V)

500k

Ω

1

2

3

4

8

7

6

5

8

7

6

5

10

µF10µF

Required for

V+ < 3.0V

+

(1.5V to 9.0V)

+

+

+

–

GS7660

GS7660

–

Oscillator Frequency Control

For normal operation, the

Boost, and Oscillator Pins

supply will increase oscillator frequency by a factor of 5,

resulting in lower Output Impedance, less ripple, smaller

required capacitor values and moves the switching noise

out of the audio band. Lower oscillator frequency reduces

quiescent current.

The oscillator frequency can be further controlled by driving

the oscillator input from an external frequency source or

lowered , by connecting an external capacitor to the oscil-

lator input.

Efficiency, Output Impedance and Output Ripple

The power efficiency of a switched capacitor voltage con-

verter is dependent on the internal losses.

The total power loss is:

(

)

1

f = f osc /2

Vripple