PM6344 datasheet(76/256 Pages) PMC

76 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

Unused

Bit 5

R/W

BPV

Bit 4

R/W

RDNINV

Bit 3

R/W

RDPINV

Bit 2

R/W

RUNI

Bit 1

R/W

RFALL

Bit 0

Unused

This register enables the Receive Interface to handle the various input waveform

formats.

BPV:

The BPV bit enables only bipolar violations to indicate line code violations

and be accumulated in the PMON LCV Count Registers. When BPV is set to

logic 1, BPVs (which are not part of a valid HDB3 signature if HDB3 line

coding is used) generate an LCV indication and increment the PMON LCV

counter. When BPV is set to logic 0, both BPVs (which are not part of a valid

HDB3 signature if HDB3 line coding is used) and excessive zeros generate

an LCV indication and increment the PMON LCV counter. Excessive zeros is

a sequence of zeros greater than 3 bits long for both AMI and HDB3 encoded

signals.

RDPINV,RDNINV:

The RDPINV and RDNINV bits enable the Receive Interface to logically invert

the signals received on multifunction pins RDP/RDD[x] and RDN/RLCV[x],

respectively. When RDPINV is set to logic 1, the interface inverts the signal on

the RDP/RDD[x] input. When RDPINV is set to logic 0, the interface passes

the RDP/RDD[x] signal unaltered. When RDNINV is set to logic 1, the

interface inverts the signal on the RDN/RLCV[x] input. When RDNINV is set

to logic 0, the interface passes the RDN/RLCV[x] signal unaltered.

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