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DM74LS461 Scheda tecnica(PDF) 1 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Il numero della parte DM74LS461
Spiegazioni elettronici  Octal Counter
PDF  4 Pages
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Produttore elettronici  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
Logo NSC - National Semiconductor (TI)

DM74LS461 Scheda tecnica(HTML) 1 Page - National Semiconductor (TI)

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TLL8334
July 1989
DM54LS461DM74LS461 Octal Counter
General Description
The LS461 is an 8-bit synchronous counter with parallel
load clear and hold capability Two function select inputs
(I0 I1) provide one of four operations which occur synchro-
nously on the rising edge of the clock (CK)
The LOAD operation loads the inputs (D7–D0) into the out-
put register (Q7–Q0) The CLEAR operation resets the out-
put register to all LOWs The HOLD operation holds the
previous value regardless of clock transitions The INCRE-
MENT operation adds one to the output register when the
carry-in input is TRUE (CI e LOW) otherwise the operation
is a HOLD The carry-out (CO) is TRUE (CO e LOW) when
the output register (Q7–Q0) is all HIGHs otherwise FALSE
(CO e HIGH)
The output register (Q7–Q0) is enabled when OE is LOW
and disabled (HI-Z) when OE is HIGH The output drivers
will sink the 24 mA required for many bus interface stand-
ards
Two or more LS461 octal counters may be cascaded to
provide larger counters The operation codes were chosen
such that when I1 is HIGH I0 may be used to select be-
tween LOAD and INCREMENT as in a program counter
(JUMPINCREMENT)
FeaturesBenefits
Y
Octal counter for microprogram-counter DMA controller
and general purpose counting applications
Y
8 bits match byte boundaries
Y
Bus-structured pinout
Y
24-pin Skinny Dip saves space
Y
TRI-STATE
outputs drive bus lines
Y
Low current PNP inputs reduce loading
Y
Expandable in 8-bit increments
Connection Diagram
Top View
TLL8334 – 1
Order Number DM54LS461J
DM74LS461J or DM74LS461N
See NS Package Number J24F or N24C
Standard Test Load
TLL8334 – 2
Function Table
OE
CK
I1
I0
CI
D7 – D0
Q7 – Q0
Operation
H
X
X
X
X
X
Z
HI-Z
L
u L L
X
X
L
CLEAR
L
u L H X
X
Q
HOLD
L
u H L
X
D
D
LOAD
L
u H H H
X
Q
HOLD
L
u H H L
X
Q plus 1
INCREMENT
TRI-STATE
is a registered trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation
RRD-B30M115Printed in U S A


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