MD1730T-VSLASHM2 datasheet(19/34 Pages) MICROCHIP

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 2016 Microchip Technology Inc.

DS20005586B-page 19

MD1730

FIGURE 4-3:

Multiple MD1730 Devices SPI Daisy Chain Connections.

4.5

CW0~7 Output Timing

The CW output waveform transmission timing is crucial

to an ultrasound imaging system. Any small timing

variations on the output can degrade the phase noise

performance. The MD1730’s internal circuitry is

designed to ensure ultra-low phase noise. Figure 4-4

shows an example of the output waveform timing

diagram. The chip is enabled by taking the EN pin high.

Then using the SPI, channel-0’s and channel-1’s phase

delay registers (PHD0<7:0> and PHD1<7:0>) are

programmed with delays of 2 and 3 respectively. The

rest of the channels are set to a high impedance state

by programming the HIZ<7:0> register with data

11111100b

. Furthermore, the frequency divider

SPI operation the transmission starts by asserting

TXRW high. The phase delay counter starts counting

down after a two CLK cycle latency. This is illustrated in

Figure 4-4 for channel 0 and channel 1. In channel 0’s

case, the phase delay starts counting down from 2 to 0

after the latency and once the delay reaches 0 on the

next rising edge of CLK, the positive output appears on

the pin CW0. Based on the value of the CWFD<7:0>

the negative supply rail. Subsequently, after 4-CLK

cycles at the negative rail, the output switches back

again to the positive supply rail, completing one full CW

output wave cycle. This process continues until the

TXRW pin deasserts low, which shuts the transmission

off and forces the channel into a high impedance state.

This same procedure applies to channel 1, which is

also depicted in Figure 4-4.

FIGURE 4-4:

CW0~7 Output Timing Diagram.

SDI

SDO

SCK

TXRW

13bit Shift Reg.

SPIB

Q12

SDI

SDO

SCK

CSN

TXRW

13bit Shift Reg.

SPIB

Q12

TXRW

SCK

CSN

SDI

FPGA

SDO

SPIB

SDI

SDO

SCK

TXXRRWW

13bit Shift Reg.

SPIB

Q12

SDI

SDO

SCK

CSN

13bit Shift Reg.

SPIB

Q12

SDI

SDO

SCK

TXXRRWW

13bit Shift Reg.

SPIB

Q12

SDI

SDO

SCK

CSN

13bit Shift Reg.

SPIB

Q12

CW0

VCW+

tdrCW

tdfCW

VCW-

t13

CLKP

Hi Z

CW end

tdrCW

CWCH = HiZ

(fCLK)

TXRW

PHD0 7:0

(Phase Delay

Time for Ch0)

TXRW

(if PHD0=2)

EN=1

tEN_ON

t14

(3-cycle CLK)

PHD1 7:0

(Phase Delay

Time for Ch1)

(if PHD1=3)

CW1

VCW+

VCW-

Hi Z

CWCH = HiZ

tdrCW

tdfCW

tdrCW

-1

PHD 7:0

Start

Count Down

(if CWFD[7:0]=4)

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