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AS4SD16M16 Scheda tecnica(PDF) 31 Page - Micross Components |
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AS4SD16M16 Scheda tecnica(HTML) 31 Page - Micross Components |
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31 / 52 page ![]() SDRAM AS4SD16M16 AS4SD16M16 Rev. 2.6 04/13/15 Micross Components reserves the right to change products or specifications without notice. 31 INITIALIZE AND LOAD MODE REGISTER2 TIMING PARAMETERS MIN MAX MIN MAX tAH 0.8 ns tCKS 1.5 ns tAS 1.5 ns tCMH 0.8 ns tCH 2.5 ns tCMS 1.5 ns tCL 2.5 ns tMRD 3 2 tCK tCK(3) 7.5 ns tRFC 66 ns tCK(2) 10 ns tRP 20 ns tCKH 0.8 ns -75 UNITS -75 SYMBOL* UNITS SYMBOL* *CAS latency indicated in parentheses. NOTES: 1. The mode register may be loaded prior to the AUTO REFRESH cycles if desired. 2. If CS is HIGH at clock HIGH time, all commands applied are NOP, with CKE a “Don’t Care”. 3. JEDEC and PC100 specify three clocks 4. Outputs are guaranteed High-Z after command is issued. 5. A12 should be a LOW at t P + 1. |
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