SDRAM

AS4SD32M16

AS4SD32M16

Rev. 2.0 10/13

Micross Components reserves the right to change products or specifications without notice.

7

COMMANDS

Truth Table 1 provides a quick reference of available

commands. This is followed by a written description of each

command. Three additional Truth Tables appear following the

Operation section; these tables provide current state/next state

information.

COMMAND INHIBIT

The COMMAND INHIBIT function prevents new

commands from being executed by the SDRAM, regardless of

whether the CLK signal is enabled. The SDRAM is effectively

deselected. Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to per-

form a NOP to an SDRAM which is selected (CS\ is LOW).

This

prevents unwanted commands from being registered

during idle or wait states. Operations already in progress are

not

affected.

LOAD MODE REGISTER

The mode register is loaded via inputs A0-A11 (A12 should

be driven LOW). See mode register heading in the Register

Definition section. The LOAD MODE REGISTER command

can only be issued when all banks are idle, and a subsequent

executable command cannot be issued until t

FUNCTION

CS\ RAS\ CAS\ WE\

DQM

ADDR

DQs

NOTES

COMMAND INHIBIT (NOP)

H

X

X

X

XXX

NO OPERATION (NOP)

L

H

H

H

XXX

ACTIVE (Select bank and activate row)

L

L

H

H

X

Bank/Row

X

3

READ (Select bank and column, and start READ burst)

LH

L

H

L/H

8

Bank/Col

X

4

WRITE (Select bank and column, and start WRITE burst)

LH

L

L

L/H

8

Bank/Col

Valid

4

BURST TERMINATE

L

H

H

L

X

X

Active

PRECHARGE (Deactivate row in bank or banks)

L

L

H

L

X

Code

X

5

AUTO REFRESH or SELF REFRESH

(Enter self refresh mode)

L

L

L

H

X

X

X

6, 7

LOAD MODE REGISTER

L

L

L

L

X

Op-Code

X

2

Write Enable/Output Enable

-

-

-

-

L

-

Active

8

Write Inhibit/Output High-Z

-

-

-

-

H

-

High-Z

8

NOTE:

1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0-A11 define the op-code written to the mode register, and A12 should be driven LOW.

3. A0-A12 provide row address, and BA0, BA1 determine which bank is made active.

4. A0-A9 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0,

BA1 determine which bank is being read from or written to.

5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

ACTIVE

The ACTIVE command is used to open (or activate) a row

in a particular bank for a subsequent access. The value on the

BA0, BA1 inputs selects the bank, and the address provided

on inputs A0-A12 selects the row. The row remains active (or

open) for accesses until a PRECHARGE command is issued to

that bank. A PRECHARGE command must be issued before

opening a different row in the same bank.

READ

The READ command is used to initiate a burst read access

to an active row. The value on the BA0, BA1 inputs selects

the bank, and the address provided on inputs A0-A8 selects the

starting column location. The value on input A10 determines

whether or not auto precharge is used. If auto precharge is

selected, the row being accessed will be precharged at the end

of the READ burst; if auto precharge is not selected, the row

will remain open for subsequent accesses. Read data appears

on the DQs subject to the logic level on the DQM inputs two

clocks earlier. If a given DQM signal was registered HIGH,

the corresponding DQs will be High-Z two clocks later; if the

DQM signal was registered LOW, the DQs will provide valid

data.

WRITE

The WRITE command is used to initiate a burst write

access to an active row. The value on the BA0, BA1 inputs