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AS5SP256K36DQ-35/IT Scheda tecnica(PDF) 1 Page - Micross Components |
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AS5SP256K36DQ-35/IT Scheda tecnica(HTML) 1 Page - Micross Components |
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1 / 14 page  COTS PEM SSRAM AS5SP256K36 AS5SP256K36 Rev. 2.2 10/13 Micross Components reserves the right to change products or specifications without notice. 1 Plastic Encapsulated Microcircuit 9.0Mb, 256K x 36, Synchronous SRAM Pipeline Burst, Single Cycle Deselect FEATURES • Synchronous Operation in relation to the input Clock • 2 Stage Registers resulting in Pipeline operation • On chip address counter (base +3) for Burst operations • Self-Timed Write Cycles • On-Chip Address and Control Registers • Byte Write support • Global Write support • On-Chip low power mode [powerdown] via ZZ pin • Interleaved or Linear Burst support via Mode pin • Three Chip Enables for ease of depth expansion without Data Contention. • Two Cycle load, Single Cycle Deselect • Asynchronous Output Enable (OE\) • Three Pin Burst Control (ADSP\, ADSC\, ADV\) • 3.3V Core Power Supply • 3.3V/2.5V IO Power Supply • JEDEC Standard 100 pin TQFP Package, • Available in Industrial, Enhanced, and Mil-Temperature Operating Ranges • RoHs compliant options available Parameter Symbol 200Mhz 166Mhz 133Mhz Units Cycle Time tCYC 5.0 6.0 7.5 ns Clock Access Time tCD 3.0 3.5 4.0 ns Output Enable Access Time tOE 3.0 3.5 4.0 ns FAST ACCESS TIMES BLOCK DIAGRAM GENERAL DESCRIPTION The AS5SP256K36 is a 9.0Mb High Performance Synchronous Pipeline Burst SRAM, available in multiple temperature screening levels, fabricated using High Performance CMOS technology and is organized as a 256K x 36. It integrates address and control registers, a two (2) bit burst address counter supporting four (4) double-word transfers. Writes are internally self-timed and synchronous to the rising edge of clock. The AS5SP256K36 includes advanced control options including Global Write, Byte Write as well as an Asynchronous Output enable. Burst Cycle controls are handled by three (3) input pins, ADV\, ADSP\ and ADSC\. Burst operation can be initiated with either the Address Strobe Processor (ADSP\) or Address Strobe controller (ADSC\) inputs. Subsequent burst addresses are generated internally in the system’s burst sequence control block and are controlled by Address Advance (ADV\) control input. CONTROL BLOCK BURST CNTL. Address Registers Row Decode Column Decode Memory Array x36 SBP I/O Gating and Control Output Register Input Register CLK CE1\ CE2 CE3\ BWE\ BWx\ GW\ ADV\ ADSC\ ADSP\ MODE A0-Ax DQx, DQP Output Driver ❑ Synchronous Pipeline Burst ❋ Two (2) cycle load ❋ One (1) cycle de-select ❋ One (1) cycle latency on Mode change OE\ ZZ DQPc DQc DQc DQc DQc DQc DQc DQd DQd DQd DQd DQd DQd DQd DQd DQc DQc DQb DQb DQb DQb DQb DQb DQb DQb DQa DQa DQa DQa DQa DQa DQa DQa DQP DQP VDD VDDQ VDD VDD VSSQ VSSQ VSSQ VSSQ VSS VDD NC VDDQ VDDQ VDDQ VDDQ VSSQ VSSQ VSSQ VSSQ SSRAM [SPB] 1 2 3 4 5 6 7 8 9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ZZ 30 29 28 27 26 25 24 23 NC NC VDD VSS 22 21 20 19 18 17 16 15 14 13 12 10 11 DQPd |
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