USB2229 datasheet(14/28 Pages) MICROCHIP

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USB2229/USB2230

DS00002252A-page 14

 2005-2016 Microchip Technology Inc.

Crystal Input/External

Clock Input

XTAL1/

CLKIN

ICLKx

24Mhz Crystal or external 24/48 MHz clock input.

This pin can be connected to one terminal of the crystal

or can be connected to an external 24/48Mhz clock when

a crystal is not used.

Note:

The ‘MA[2:0] pins will be sampled while nRE-

SET is asserted, and the value will be latched

upon nRESET negation. This will determine

the clock source and value.

Crystal Output

XTAL2

OCLKx

24Mhz Crystal

This is the other terminal of the crystal, or left open when

an external clock source is used to drive XTAL1/CLKIN.

It may not be used to drive any external circuitry other

than the crystal circuit.

MEMORY/IO INTERFACE

Memory Data Bus

MD[7:0]

IO8

When ROMEN bit of GPIO_IN1 register = 0, these

signals are used to transfer data between the internal

CPU and the external program memory.

These pins have internally controlled weak pull-up

resistors.

Memory Address Bus

MA[15:3]

These signals address memory locations within the

external memory.

Memory Address Bus

MA3/

TX_POL

I/O8PU

MA3 Addresses memory locations within the external

memory.

During nRESET assertion, TX_POL will select the

operating polarity of the IR LED (active high or active low)

and the weak pull-up resistor will be enabled. When

nRESET is negated, the value on this pin will be internally

latched and this pin will revert to MA3 functionality, the

internal pull-up will be disabled.

Memory Address Bus

MA2/

SEL_CLKDRV

I/O8PD

MA2 Addresses memory locations within the external

memory.

SEL_CLKDRV. During nRESET assertion, this pins will

select the operating clock mode (crystal or externally

driven clock source), and a weak pull-down resistor is

enabled. When nRESET is negated, the value will be

internally latched and this pin will revert to MA2

functionality, the internal pull-down will be disabled.

‘0’ = Crystal operation (24MHz only)

‘1’ = Externally driven clock source (24MHz or 48MHz)

Note:

If the latched value is ‘1’, then the MA2 pin is

tri-stated when the following conditions are

true:

1. IDLE bit (PCON.0) is 1.

2. INT2 is negated

3. SLEEP bit of CLOCK_SEL is 1.

If the latched value is ‘0’, then the MA2 pin will function

identically to the MA[15:3] pins at all times (other than

during nRESET assertion).

TABLE 5-1:

USB2229/USB2230 PIN DESCRIPTIONS (CONTINUED)

Name

Symbol

Buffer Type

Description

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