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LAN8741Ai-EN Scheda tecnica(PDF) 91 Page - Microchip Technology |
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LAN8741Ai-EN Scheda tecnica(HTML) 91 Page - Microchip Technology |
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91 / 106 page ![]() 2013-2015 Microchip Technology Inc. DS00001988A-page 91 LAN8741A/LAN8741Ai 5.6.3.1 100 Mbps Internal Loopback MII Timing FIGURE 5-5: 100 MBPS INTERNAL LOOPBACK MII TIMING TABLE 5-11: 100 MBPS INTERNAL LOOPBACK MII TIMING VALUES Symbol Description Min. Typ. Max. Unit t1 TXCLK rising edge after TXEN assertion to RXDV assertion (100 Mbps internal loopback MII mode) 160 161 162 ns Note: The t1 measurement applies in MII mode when the Loopback bit of the Basic Control Register is set to “1” and a link has been established in 100 Mb full-duplex mode. The t1 measurement is taken from the first rising edge of TXCLK following assertion of TXEN to the rising edge of RXDV. TXCLK (OUTPUT) RXD[3:0] (OUTPUTS) TXEN (INPUT) t1 RXDV (OUTPUT) |
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