ARM920T datasheet(4/12 Pages) ETC

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The ARMv4T Architecture

Page 4

DVI 0024A

ARM Confidential - Draft

Registers

The ARM9TDMI processor core

consists of a 32-bit datapath and

associated control logic. That

datapath contains 31 general-

purpose registers, coupled to a full

shifter, Arithmetic Logic Unit, and

multiplier. At any one time 16

registers are visible to the user. The

remainder are synonyms used to

speed up exception processing.

Program Counter

(PC) and can be used in all

instructions to reference data relative

to the current instruction. R14 holds

the return address after a subroutine

call. R13 is used (by software

convention) as a stack pointer.

Modes and exception

handling

All exceptions have banked registers

for R14 and R13. After an exception,

R14 holds the return address for

exception processing. This address

is used both to return after the

exception is processed and to

address the instruction that caused

the exception. R13 is banked across

exception modes to provide each

exception handler with a private

stack pointer. The fast interrupt mode

also banks registers 8 to 12 so that

interrupt processing can begin

without the need to save or restore

these registers. A seventh

processing mode, System mode,

does not have any banked registers.

It uses the User mode registers.

System mode runs tasks that require

a privileged processor mode and

allows them to invoke all classes of

exceptions.

Status registers

All other processor states are held in

status registers. The current

operating processor status is in the

Current Program Status Register

(CPSR). The CPSR holds:

•

four ALU flags (Negative, Zero,

Carry, and Overflow),

•

two interrupt disable bits (one for

each type of interrupt),

•

a bit to indicate ARM or Thumb

execution,

•

and five bits to encode the

current processor mode.

All five exception modes also have a

Saved Program Status Register

(SPSR) which holds the CPSR of the

task immediately before the

exception occurred.

Exception types

ARM9TDMI supports five types of

exception, and a privileged

processing mode for each type. The

types of exceptions are:

•

fast interrupt (FIQ)

•

normal interrupt (IRQ)

•

memory aborts (used to

implement memory protection or

virtual memory)

•

attempted execution of an

undefined instruction

•

software interrupts (SWIs).

Conditional execution

All ARM instructions (with the

exception of BLX) are conditionally

executed. Instructions optionally

update the four condition code flags

(Negative, Zero, Carry, and

Overflow) according to their result.

Subsequent instructions are

conditionally executed according to

the status of flags. Fifteen conditions

are implemented.

Four classes of

instructions

The ARM and Thumb instruction sets

can be divided into four broad

classes of instruction:

•

data processing instructions

•

load and store instructions

•

branch instructions

•

coprocessor instructions.

Data processing

The data processing instructions

operate on data held in general

purpose registers. Of the two source

operands, one is always a register.

The other has two basic forms:

•

an immediate value

•

a register value optionally

shifted.

If the operand is a shifted register the

shift amount might have an

immediate value or the value of

another register. Four types of shift

can be specified. Most data

processing instructions can perform

a shift followed by a logical or

arithmetic operation. Multiply

instructions come in two classes:

•

normal - 32-bit result

•

long - 32-bit result variants.

Both types of multiply instruction can

optionally perform an accumulate

operation.

Load and store

The second class of instruction is

load and store instructions. These

instructions come in two main types:

•

load or store the value of a single

•

load and store multiple register

values.

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