LM359 datasheet(12/24 Pages) NSC

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Application Hints (Continued)

DESIGN EXAMPLE:

IN = 50 mV (MAX), fIN = 10 MHz (MAX), desired circuit

BW = 20 MHz, A

V = 20 dB, driving source impedance =

Ω,V+ = 12V.

Basic circuit configuration:

Select I

SET to provide adequate amplifier bandwidth so

that the closed loop bandwidth will be determined by R

and C

f. To do this, the set current should program an

amplifier open loop gain of at least 20 dB at the desired

closed loop bandwidth of the circuit. For this example,

an I

SET of 0.5 mA will provide 26 dB of open loop gain at

20 MHz which will be sufficient. Using single resistor pro-

gramming for I

SET:

Since the closed loop bandwidth will be determined by

to obtain a 20 MHz bandwidth, both R

f and Cf should be kept

small. It can be assumed that C

f can be in the range of 1 pF

to 5 pF for carefully constructed circuit boards to insure sta-

bility and allow a flat frequency response. This will limit the

value of R

f to be within the range of:

Also, for a closed loop gain of +10, R

f must be 10 times Rs

e where re is the mirror diode resistance.

So as not to appreciably load the 75

Ω input termination

resistance the value of (R

s +re) is set to 750Ω.

For A

v = 10; Rf is set to 7.5 kΩ.

The optimum output DC level for symmetrical AC swing

is:

The DC feedback current must be:

DC biasing predictability will be insured because 640 µA is

greater than the minimum of I

SET/5 or 100 µA.

For gain accuracy the total AC and DC mirror current should

be less than 2 mA. For this example the maximum AC mirror

current will be:

therefore the total mirror current range will be 574 µA to 706

µA which will insure gain accuracy.

b can now be found:

Since R

s +re will be 750Ω and re is fixed by the DC mir-

ror current to be:

s must be 750Ω–40Ω or 710Ω which can be a 680Ω resis-

tor in series with a 30

Ω resistor which are standard 5% toler-

ance resistor values.

10. As a final design step, C

i must be selected to pass the

lower passband frequency corner of 8 Hz for this ex-

ample.

A larger value may be used and a 0.01 µF ceramic capacitor

in parallel with C

i will maintain high frequency gain accuracy.

DS007788-20

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