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LAN9250 Scheda tecnica(PDF) 207 Page - Microchip Technology

Il numero della parte LAN9250
Spiegazioni elettronici  Integrated Ethernet PHY with HP Auto-MDIX
PDF  421 Pages
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Produttore elettronici  MICROCHIP [Microchip Technology]
Homepage  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9250 Scheda tecnica(HTML) 207 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001913A-page 207
LAN9250
11.15.13 HOST MAC CHECKSUM OFFLOAD ENGINE CONTROL REGISTER (HMAC_COE_CR)
This register controls the RX and TX checksum offload engines.
Offset:
0Dh
Size:
32 bits
Bits
Description
Type
Default
31:17
RESERVED
RO
-
16
TX Checksum Offload Engine Enable (TX_COE_EN)
TX_COE_EN may only be changed if the TX path is disabled. If it is desired
to change this value during run time, it is safe to do so only after the Host
MAC is disabled and the TLI is empty.
0 = The TXCOE is bypassed
1 = The TXCOE is enabled
R/W
0b
15:2
RESERVED
RO
-
1
RX Checksum Offload Engine Mode (RX_COE_MODE)
This register indicates whether the COE will check for VLAN tags or a SNAP
header prior to beginning its checksum calculation. In its default mode, the
calculation will always begin 14 bytes into the frame.
RX_COE_MODE may only be changed if the RX path is disabled. If it is
desired to change this value during run time, it is safe to do so only after the
Host MAC is disabled and the TLI is empty.
0 = Begin checksum calculation after first 14 bytes of Ethernet Frame
1 = Begin checksum calculation at start of L3 packet by adjusting for
VLAN tags and/or SNAP header.
R/W
0b
0
RX Checksum Offload Engine Enable (RX_COE_EN)
RX_COE_EN may only be changed if the RX path is disabled. If it is desired
to change this value during run time, it is safe to do so only after the Host
MAC is disabled and the TLI is empty.
0 = The RXCOE is bypassed
1 = The RXCOE is enabled
R/W
0b



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