MCP6V64 datasheet(21/46 Pages) MICROCHIP

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DS20005367B-page 21

MCP6V61/1U/2/4

4.3.4

SOURCE RESISTANCES

The input bias currents have two significant

components: switching glitches that dominate at room

temperature and below and input ESD diode leakage

currents that dominate at +85°C and above.

Make the resistances seen by the inputs small and

equal. This minimizes the output offset caused by the

input bias currents.

The inputs should see a resistance on the order of 10Ω

to 1 kΩ at high frequencies (i.e., above 1 MHz). This

helps minimize the impact of switching glitches, which

are very fast, on overall performance. In some cases it

may be necessary to add resistors in series with the

inputs to achieve this improvement in performance.

Small input resistances may be needed for high gains.

Without them, parasitic capacitances might cause

positive feedback and instability.

4.3.5

SOURCE CAPACITANCE

The capacitances seen by the two inputs should be

small.

Large

input

capacitances

and

source

resistances, together with high gain, can lead to

positive feedback and instability.

4.3.6

CAPACITIVE LOADS

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response. These zero-drift op amps have a different

output impedance than most op amps, due to their

unique topology.

When driving a capacitive load with these op amps, a

series resistor at the output (RISO in Figure 4-7)

improves the feedback loop’s phase margin (stability)

by making the output load resistive at higher

frequencies. The bandwidth will be generally lower

than the bandwidth with no capacitive load.

FIGURE 4-7:

Output Resistor, RISO,

Stabilizes Capacitive Loads.

Figure 4-8 gives recommended RISO values for

different capacitive loads and gains. The x-axis is the

load capacitance (CL). The y-axis is the resistance

(RISO).

GN is the circuit’s noise gain. For non-inverting gains,

GN and the Signal Gain are equal. For inverting gains,

GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).

FIGURE 4-8:

Recommended RISO values

for Capacitive Loads.

After selecting RISO for your circuit, double check the

resulting frequency response peaking and step

response overshoot. Modify the RISO value until the

response is reasonable. Bench evaluation is helpful.

4.3.7

STABILIZING OUTPUT LOADS

This family of zero-drift op amps has an output

impedance (Figures 2-32 and 2-33) that has a double

zero when the gain is low. This can cause a large phase

shift in feedback networks that have low-impedance

near the part’s bandwidth. This large phase shift can

cause stability problems.

Figure 4-9 shows that the load on the output is

(RL +RISO)||(RF +RG), where RISO is before the load

(like Figure 4-7). This load needs to be large enough to

maintain stability; it should be at least 10 kΩ.

FIGURE 4-9:

Output Load.

RISO

VOUT

MCP6V6X

100

1000

10000

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

Normalized Load Capacitance; C

L/ GN (F)

1 V/V

10 V/V

100 V/V

DD = 5.5V

L = 20 k

100p

10n

100n

1µ

VOUT

MCP6V6X

RISO

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