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STW4510 Scheda tecnica(PDF) 32 Page - STMicroelectronics |
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STW4510 Scheda tecnica(HTML) 32 Page - STMicroelectronics |
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32 / 57 page ![]() Obsolete Product(s) - Obsolete Product(s) Functional description STw4510 32/57 3.3.5 Vana2 This LDO is dedicated, for example, to supply an analog part of a peripheral associated to a processor. Main features ● Programmable output voltage: Vana2_sel[1:0] pads 1.8 V, 2.8 V, 3.0 V, 3.3 V (to be fixed in the application by routing to Vbat or ground). On the 4 mm x 4 mm package the selection of output voltage values is limited to Sel[0] and the available voltage values are 3.0 V and 3.3 V” ● Three power domains: – High power mode, 150 mA full load – Sleep mode with a low current capability of 0.5 mA full load ( Table 21) – Power down mode when regulator is switched off and there is no power consumption (pdn-vana2 bit of application control register ( Application control register 1) or en_vana2 bit of power control register - (Power control register @ 08h), it is recommended to use only the pdn_vana2 control bit. ● Default setting defined by start-up device configuration ● Specification guaranteed with battery voltages from 2.7 V up to 5.5 V (with a minimum battery voltage of 3.0 V for a LDO output of 2.8 V) Note: The definition of sleep mode is given in Section 3.2.3. 3.3.6 Vana3 This LDO is dedicated, for example, to supply a critical stage like a PLL of a processor or an analog part of a peripheral associated to a processor Main features ● Programmable output voltage: Vana3_sel[1:0] pads - 1.8 V, 2.8 V, 3.0 V, 3.3 V (to be fixed in the application by routing to Vbat or ground). ground. On the 4 mm x 4 mm package the selection of output voltage values has been limited to Sel[0] and the available voltage values are 3.0 V and 3.3 V. ● Three power domains: – High power mode, 150 mA full load – Sleep mode with a low current capability of 0.5 mA full load ( Table 21) – Power down mode when regulator is switched off and there is no power consumption (pdn-vana3 bit of application control register ( Application control register 1) or en_vana3 bit of power control register - Power control register @ 07h), it is recommended to use only the pdn_vana3 control bit. ● Default setting defined by start-up configuration ● Specification guaranteed with battery voltages from 2.7 V up to 5.5 V (with a minimum battery voltage of 3.5V for a LDO output of 3.3 V with the full characteristics available) Note: The definition of sleep mode is given in Section 3.2.3. |
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