X84256S16 datasheet(2/15 Pages) XICOR

2 / 15 page

X84256

Preliminary

PIN CONFIGURATIONS

Drawings are to the same scale, actual package sizes are

shown in inches:

PIN NAMES

PIN DESCRIPTIONS

Chip Enable (CE)

The Chip Enable input must be LOW to enable all read/

write operations. When CE is HIGH, the chip is dese-

lected, the I/O pin is in the high impedance state, and

unless a nonvolatile write operation is underway, the

device is in the standby power mode.

Output Enable (OE)

The Output Enable input must be LOW to enable the out-

put buffer and to read data from the device on the I/O line.

Write Enable (WE)

The Write Enable input must be LOW to write either data

or command sequences to the device.

Data In/Data Out (I/O)

Data and command sequences are serially written to or

serially read from the device through the I/O pin.

Write Protect (WP)

When the Write Protect input is LOW, nonvolatile writes to

the device are disabled. When WP is HIGH, all functions,

including nonvolatile writes, operate normally. If a nonvol-

atile write cycle is in progress, WP going LOW will have

no effect on the cycle already underway, but will inhibit

any additional nonvolatile write cycles.

DEVICE OPERATION

The X84256 serial EEPROM is designed to interface

directly with most microprocessor buses. Standard CE,

OE, and WE signals control the read and write opera-

tions, and a single l/O line is used to send and receive

data and commands serially.

VCC

I/O

VSS

8-LEAD SOIC

14-LEAD TSSOP

I/O

VSS

VCC

I/O

VCC

VSS

8-LEAD XBGA

X84256

16-LEAD SOIC

I/O

VSS

VCC

I/O

Data Input/Output

Chip Enable Input

Output Enable Input

Write Enable Input

Write Protect Input

VCC

Supply Voltage

VSS

Ground

No Connect

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