LM4872 datasheet(13/14 Pages) NSC

13 / 14 page

Application Information (Continued)

REFERENCE DESIGN BOARD and PCB LAYOUT

GUIDELINES

PCB Layout Guidelines

This section provides practical guidelines for mixed signal

PCB layout that involves various digital/analog power and

ground traces. Designers should note that these are only

″rule-of-thumb″ recommendations and the actual results will

depend heavily on the final layout.

General Mixed Signal Layout Recommendation

Power and Ground Circuits

For 2 layer mixed signal design, it is important to isolate the

digital power and ground trace paths from the analog power

and ground trace paths. Star trace routing techniques (bring-

ing individual traces back to a central point rather than daisy

chaining traces together in a serial manner) can have a ma-

jor impact on low level signal performance. Star trace routing

refers to using individual traces to feed power and ground to

each circuit or even device. This technique will take require

a greater amount of design time but will not increase the final

price of the board. The only extra parts required will be some

jumpers.

Single-Point Power / Ground Connections

The analog power traces should be connected to the digital

traces through a single point (link). A

″Pi-filter″ can be helpful

in minimizing High Frequency noise coupling between the

analog and digital sections. It is further recommended to put

digital and analog power traces over the corresponding digi-

tal and analog ground traces to minimize noise coupling.

Placement of Digital and Analog Components

All digital components and high-speed digital signals traces

should be located as far away as possible from analog com-

ponents and circuit traces.

Avoiding Typical Design / Layout Problems

Avoid ground loops or running digital and analog traces par-

allel to each other (side-by-side) on the same PCB layer.

When traces must cross over each other do it at 90 degrees.

Running digital and analog traces at 90 degrees to each

other from the top to the bottom side as much as possible will

minimize capacitive noise coupling and cross talk.

DS101230-25

Figure 4

LM4872 Scheda tecnica(PDF) 13 Page - National Semiconductor (TI)

LM4872 Scheda tecnica(HTML) 13 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Scheda tecnica Scarica

Link URL