CD54HC4046AF datasheet(20/28 Pages) TI

20 / 28 page

PLL Conditions with

No Signal at the

SIGIN Input

PC1

VCO adjusts to fo with φDEMOUT = 90

o and V

VCOIN = 1/2 VCC (see Figure 2)

PC2

VCO adjusts to fMIN with φDEMOUT = -360

o and V

VCOIN = 0V (see Figure 4)

PC3

VCO adjusts to fMAX with φDEMOUT = 360

o and V

VCOIN = VCC (see Figure 6)

PLL Frequency

Capture Range

PC1, PC2 or PC3

Loop Filter Component Selection

PLL Locks on

Harmonics at Center

Frequency

PC1 or PC3

Yes

PC2

Noise Rejection at

Signal Input

PC1

High

PC2 or PC3

Low

AC Ripple Content

when PLL is Locked

PC1

fr = 2fi, large ripple content at φDEMOUT = 90

PC2

fr = fi, small ripple content at φDEMOUT = 0

PC3

fr = fSIGIN, large ripple content at φDEMOUT = 180

SUBJECT

PHASE

COMPARATOR

DESIGN CONSIDERATIONS

A small capture range (2fc) is obtained if τ > 2fc ≈ 1/π (2πfL/τ.)

1/2

FIGURE 46. SIMPLE LOOP FILTER FOR PLL WITHOUT OFFSET

(A)

τ = R3 x C2

(B) AMPLITUDE CHARACTERISTIC

INPUT

OUTPUT

|F(j

ω)|

-1/

FIGURE 47. SIMPLE LOOP FILTER FOR PLL WITH OFFSET

(A)

τ1 = R3 x C2;

(B) AMPLITUDE CHARACTERISTIC

|F(j

ω)|

-1/

τ2

INPUT

OUTPUT

τ2 = R4 x C2;

τ3 = (R3 + R4) x C2

-1/

τ3

τ3 1/τ2

m =

R3 + R4

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

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