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MB91F465KB Scheda tecnica(PDF) 1 Page - Cypress Semiconductor |
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MB91F465KB Scheda tecnica(HTML) 1 Page - Cypress Semiconductor |
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1 / 86 page  MB91F465KA MB91F465KB FR60, MB91460K Series, 32-bit Microcontroller Datasheet Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 002-04602 Rev. *A Revised April 14, 2016 MB91460K series is a line of general-purpose 32-bit RISC microcontrollers designed for embedded control applications which require high-speed real-time processing, such as consumer devices and on-board vehicle systems. This series uses the FR60 CPU, which is compatible with the FR family of CPUs. This series contains the LIN-USART and CAN controllers. Features FR60 CPU core ■ 32-bit RISC, load/store architecture, five-stage pipeline ■ 16-bit fixed-length instructions (basic instructions) ■ Instruction execution speed: 1 instruction per cycle ■ Instructions including memory-to-memory transfer, bit manip- ulation, and barrel shift instructions: Instructions suitable for embedded applications ■ Function entry/exit instructions and register data multi-load store instructions : Instructions supporting C language ■ Register interlock function: Facilitating assembly-language coding ■ Built-in multiplier with instruction-level support Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles ■ Interrupts (save PC/PS): 6 cycles (16 priority levels) ■ Harvard architecture enabling program access and data access to be performed simultaneously ■ Instructions compatible with the FR family Internal peripheral resources ■ General-purpose ports: Maximum 73 ports ■ DMAC (DMA Controller) ■ Maximum of 5 channels able to operate simultaneously. ■ 2 transfer sources (internal peripheral/software) ■ Activation source can be selected using software. ■ Addressing mode specifies full 32-bit addresses (increment/decrement/fixed) ■ Transfer mode (demand transfer/burst transfer/step transfer/block transfer) ■ Transfer data size selectable from 8/16/32-bit ■ Multi-byte transfer enabled (by software) ■ DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H) ■ A/D converter (successive approximation type) ■ 10-bit resolution: 26 channels ■ Conversion time: minimum 1 s ■ External interrupt inputs: 10 channels ■ Shares the CAN RX pin and the I2C SDA pin ■ Bit search module (for REALOS) ■ Function to search from the MSB (most significant bit) for the position of the first “0”, “1”, or changed bit in a word ■ LIN-USART (full duplex double buffer): 5 channels ■ Clock synchronous/asynchronous selectable ■ Sync-break detection ■ Internal dedicated baud rate generator ■ I2C bus interface (supports 400 kbps): 1 channel ■ Master/slave transmission and reception ■ Arbitration function, clock synchronisation function ■ CAN controller (C-CAN): 1 channel ■ Maximum transfer speed: 1 Mbps ■ 32 transmission/reception message buffers ■ 16-bit PPG timer: 12 channels ■ 16-bit reload timer: 8 channels ■ 16-bit free-run timer: 8 channels (1 channel each for ICU and OCU) ■ Input capture: 8 channels (operates in conjunction with the free-run timer) ■ Output compare: 8 channels (operates in conjunction with the free-run timer) ■ Watchdog timer ■ Real-time clock ■ Low-power consumption modes : Sleep/stop mode function ■ Supply Supervisor: Low voltage detection circuit for external VDD5 and internal 1.8V core voltage ■ Clock supervisor Monitors the sub-clock (32 kHz) and the main clock (4 MHz) , |
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