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34RC02 Scheda tecnica(PDF) 3 Page - Catalyst Semiconductor

Il numero della parte 34RC02
Spiegazioni elettronici  2-kb I2C Serial EEPROM, Serial Presence Detect
PDF  16 Pages
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Produttore elettronici  CATALYST [Catalyst Semiconductor]
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34RC02 Scheda tecnica(HTML) 3 Page - Catalyst Semiconductor

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CAT34RC02
3
Doc No. 1052, Rev. K
Write Cycle Limits
Symbol
Parameter
Min
Typ
Max
Units
tWR
Write Cycle Time
5
ms
A.C. CHARACTERISTICS
VCC = 1.7 V to 5.5 V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
1.7 V - 5.5 V
2.5 V - 5.5 V
Min
Max
Min
Max
Units
FSCL
Clock Frequency
100
400
kHz
TI(1)
Noise Suppression Time
100
100
ns
Constant at SCL, SDA Inputs
tAA
SCL Low to SDA Data Out
3.5
0.9
µs
and ACK Out
tBUF(1)
Time the Bus Must be Free Before
4.7
1.3
µs
a New Transmission Can Start
tHD:STA
Start Condition Hold Time
4
0.6
µs
tLOW
Clock Low Period
4.7
1.3
µs
tHIGH
Clock High Period
4
0.6
µs
tSU:STA
Start Condition Setup Time
4.7
0.6
µs
(for a Repeated Start Condition)
tHD:DAT
Data In Hold Time
0
0
ns
tSU:DAT
Data In Setup Time
250
100
ns
tR(1)
SDA and SCL Rise Time
1
0.3
µs
tF(1)
SDA and SCL Fall Time
300
300
ns
tSU:STO
Stop Condition Setup Time
4
0.6
µs
tDH
Data Out Hold Time
100
100
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Power-Up Timing(1)(2)
Symbol
Parameter
Min
Typ
Max
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
The write cycle time is the time elapsed between the
STOP command (following the write instruction) and the
completion of the internal write cycle. During the internal
write cycle, SDA is released by the Slave and the device
does not acknowledge external commands.



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