19

Integrated

Circuit

Systems, Inc.

ICS952601

0701G—10/13/04

The following diagrams illustrate CPU clock timing during CPU_Stop# and PwrDwn# modes with CPU_PwrDwn and

CPU_Stop tristate control bits set to driven or tristate in byte 2 of the control register.

CPU_Stop = Driven, CPU_Pwrdwn = Driven

CPU_Stop#

1.8mS

PD#

CPU (Free Running)

CPU# (Free Running)

CPU (Stoppable)

CPU# (Stoppable)

Notes:

1. When both bits (CPU_Stop & CPU_Pwrdown tristate bits) are low, the clock chip will never tristate CPU output clocks

(assuming clock's OE bit is set to "1")

CPU Clock Tristate Timing

CPU_Stop = Tristate, CPU_Pwrdwn = Driven

CPU_Stop#

1.8mS

PD#

CPU (Free Running)

CPU# (Free Running)

CPU (Stoppable)

CPU# (Stoppable)

Notes:

1. Tristate outputs are pulled low by output termination resistors as shown here.