CAT64LC40LITE13 datasheet(8/12 Pages) CATALYST

8 / 12 page

Discontinued

Parts

CAT64LC10/20/40

Doc. No. 1021, Rev. C

WRITE cycle. The RDY/

BSY pin will output the BUSY

status (LOW) one tSV after the rising edge of the 32nd

clock (the last data bit) and will stay LOW until the write

cycle is complete. Then it will output a logical “1” until the

next WRITE cycle. The RDY/

BSY output is not affected

by the input of

CS.

An alternative to get RDY/

BSY status is from the DO pin.

During a write cycle, asserting a LOW input to the

CS pin

will cause the DO pin to output the RDY/

BSY status.

Bringing

CS HIGH will bring the DO pin back to a high

impedance state again. After the device has completed

a WRITE cycle, the DO pin will output a logical “1” when

the device is deselected. The rising edge of the first “1”

input on the DI pin will reset DO back to the high

impedance state again.

The WRITE operation can be halted anywhere in the

operation by the RESET input. If a RESET pulse occurs

during a WRITE operation, the device will abort the

operation and output a READY status.

NOTE: Data may be corrupted if a RESET occurs while

the device is

BUSY. If the reset occurs before the BUSY

period, no writing will be initiated. However, if RESET

occurs after the

BUSY period, new data will have been

written over the old data.

Figure 6. RESET During

BUSY

BUSY Instruction Timing

Figure 7. EWEN Instruction Timing

5064 FHD F09

* Please check instruction set table for address

RESET

10100100

ADDRESS*

D15

tWR

RDY/

BUSY

RESET

10100011

HIGH-Z

HIGH

RDY/

BUSY

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