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NON-INVERTING SINGLE-SUPPLY OPERATION

1

2

4

3

5

FB2

GND

GND

J3

J4

J6

J5

GND

TP1

C2

3.3 mF

C4

0.1 mF

NC

C8

R8

249 W

249 W

R7

U1

J1

C7

R10

0

0

R1

49.9 W

THS4304DBV

R2

49.9 W

C9

0

J2

R3

10 kW

10 kW

R6

0.1 mF

C5

0

3

4

1

5

2

+

−

DIFFERENTIAL ADC DRIVE AMPLIFIER

THS4304

SLOS436A – MARCH 2004 – REVISED JULY 2004

The THS4304 EVM can easily be configured for single 5-V supply operation, as shown in the following

schematic, with no change in performance. This circuit passes dc signals at the input, so care must be taken to

reference (or bias) the input signal to mid-supply.

If dc operation is not required, the amplifier can be ac coupled by inserting a capacitor in series with the input

(C7) and output (C9).

Figure 54. Non-Inverting 5-V Single-Supply Amplifier

The circuit shown in Figure 54 is adapted as shown in Figure 55 to provide a high-performance differential

amplifier drive circuit for use with high-performance ADCs, like the ADS5500 (14-bit 125-MSP ADC). For testing

purposes, the circuit uses a transformer to convert the signal from a single-ended source to differential. If the

input signal source in your application is differential and biased to mid-rail, no transformer is required.

The circuit employs two amplifiers to provide a differential signal path to the ADS5500. A resistor divider (two

10-k

Ω resistors) is used to obtain a mid-supply reference voltage of 2.5 V (VREF) (the same as shown in the

single-supply circuit of Figure 54). Applying this voltage to the one side of RG and to the positive input of the

operational amplifier (via the center-tap of the transformer) sets the input and output common-mode voltage of

the operational amplifiers to mid-rail to optimize their performance. The ADS5500 requires an input

common-mode voltage of 1.5 V. Due to the mismatch in required common-mode voltage, the signal is ac coupled

from the amplifier output, via the two 1-nF capacitors, to the input of the ADC. The CM voltage of the ADS5500 is

used to bias the ADC input to the required voltage, via the 1-k

Ω resistors. Note: 100-µA common-mode current is

drawn by the ADS5500 input stage (at 125 MSPS). This causes a 100-mV shift in the input common-mode

voltage, which does not impact the performance when driving the input to –1 dB of full scale. To offset this effect,

a voltage divider from the power supply can be used to derive the input common-mode voltage reference.

Because the operational amplifiers are configured as non-inverting, the inputs are high impedance. This is

particularly useful when interfacing to a high-impedance source. In this situation, the amplifiers provide

impedance matching and amplification of the signal.

The SFDR performance of the circuit is shown in the following graph (see Figure 56) and provides for full

performance from the ADS5500 to 40 MHz.

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