Two-Wire Serial Communication Interface Switching Characteristics

Unless otherwise noted, below specifications apply for V

pacitance on output lines can be up to 400pF provided that external pull-up is on board. The following parameters are the tim-

ing relationship between SCL and SDA signals related to the DS90C2501.

Symbol

Parameter

Min

Typ

Max

Units

t

1

SCL (Clock) Period

2.5

2000

(Note 7)

µs

t

2

Data in Set-Up Time to SCL High

100

ns

t

3

Data Out Stable after SCL Low

0

ns

t

4

SDA Low Set-Up Time to SCL Low (Start Condition)

100

ns

t

5

SDA High Hold Time after SCL High (Stop Condition)

100

ns

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device

should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.

Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise

Note 4: The limits are based on bench characterization of the device’s jitter response over the power supply voltage range. Output clock jitter is measured with a

calculating system margin as described in AN-1059.

Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output pulse positions

(min and max) and the receiver input setup and hold time (internal data sampling window - RSPOS). This margin allows for LVDS interconnect skew, inter-symbol

interference (both dependent on type/length of cable) and clock jitter.

RSKM

≥ cable skew (type, length) + source clock jitter (cycle to cycle).

Note 7: Guaranteed by Design

AC Timing Diagrams

20004532

FIGURE 1. “Alternate High/Low” Test Pattern in 12-bit Input Mode (Note 8)

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