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LMX1501 Scheda tecnica(PDF) 18 Page - National Semiconductor (TI) |
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LMX1501 Scheda tecnica(HTML) 18 Page - National Semiconductor (TI) |
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18 / 22 page ![]() Application Information (Continued) TLW12340 – 43 FIGURE 5 PLL Reference Spurs The reference spurious level is k b66 dBc due to the loop filter attenuation and the low spurious noise level of the LMX1511 TLW12340 – 45 FIGURE 6 PLL Phase Noise 35 kHz Offset The phase noise level at 3 kHz offset is b65 dBcHz TLW12340 – 44 FIGURE 7 PLL Phase Noise 150 Hz Offset The phase noise level at 150 Hz offset is b755 dBcHz TLW12340 – 42 FIGURE 8 Frequency Jump Lock Time Of concern in any PLL loop filter design is the time it takes to lock in to a new frequency when switching channels Fig- ure 8 shows the switching waveforms for a frequency jump of 857 MHz – 915 MHz By narrowing the frequency span of the HP53310A Modulation Domain Analyzer enables evalu- ation of the frequency lock time to within g1 kHz The lock time is seen to be k 16 ms for a frequency jump of 58 MHz 18 |
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