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P3056LS Scheda tecnica(PDF) 2 Page - List of Unclassifed Manufacturers

Il numero della parte P3056LS
Spiegazioni elettronici  N-Channel Logic Level Enhancement Mode Field Effect Transistor
PDF  3 Pages
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Produttore elettronici  ETC [List of Unclassifed Manufacturers]
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P3056LS Scheda tecnica(HTML) 2 Page - List of Unclassifed Manufacturers

  P3056LS Datasheet HTML 1Page - List of Unclassifed Manufacturers P3056LS Datasheet HTML 2Page - List of Unclassifed Manufacturers P3056LS Datasheet HTML 3Page - List of Unclassifed Manufacturers  
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AUG-09-2001
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P3056LS
TO-263
NIKO-SEM
On-State Drain Current
1
ID(ON)
VDS = 10V, VGS = 10V
12
A
VGS = 5V, ID = 12A
70
120
Drain-Source On-State
Resistance
1
RDS(ON)
VGS = 10V, ID = 12A
50
90
m
Ω
Forward Transconductance
1
gfs
VDS = 15V, ID = 12A
16
S
DYNAMIC
Input Capacitance
Ciss
450
Output Capacitance
Coss
200
Reverse Transfer Capacitance
Crss
VGS = 0V, VDS = 15V, f = 1MHz
60
pF
Total Gate Charge
2
Qg
15
Gate-Source Charge
2
Qgs
2.0
Gate-Drain Charge
2
Qgd
VDS = 0.5V(BR)DSS, VGS = 10V,
ID = 6A
7.0
nC
Turn-On Delay Time
2
td(on)
6.0
Rise Time
2
tr
VDS = 15V, RL = 1Ω
6.0
Turn-Off Delay Time
2
td(off)
ID
≅ 12A, V
GS = 10V, RGS = 2.5Ω
20
Fall Time
2
tf
5.0
nS
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C)
Continuous Current
IS
12
Pulsed Current
3
ISM
20
A
Forward Voltage
1
VSD
IF = IS, VGS = 0V
1.5
V
Reverse Recovery Time
trr
30
nS
Peak Reverse Recovery Current
IRM(REC)
IF = IS, dlF/dt = 100A /
µS
15
A
Reverse Recovery Charge
Qrr
0.043
µC
1Pulse test : Pulse Width
≤ 300 µsec, Duty Cycle ≤ 2%.
2Independent of operating temperature.
3Pulse width limited by maximum junction temperature.
REMARK: THE PRODUCT MARKED WITH “P3056LS”, DATE CODE or LOT #



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