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LP3927 Scheda tecnica(PDF) 12 Page - National Semiconductor (TI) |
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LP3927 Scheda tecnica(HTML) 12 Page - National Semiconductor (TI) |
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12 / 16 page ![]() VEXT Detect Start-Up/Shut Down 20037927 Note: Diagram indicates Open Drain IRQ tied to VDD. *** = Internal signal 1. VEXT goes active low. 2. VEXT 32 msec de-bounce period. 3. Delay between LDO1 and LDO2 enables. 4. Both LDO1 and LDO2 outputs reach 95% of respective output voltage, start Reset timer. 5. Reset delay. 6. Period between Reset and PS_HOLD going high is not relevant since VEXT is low 7. PS_HOLD goes low but LDOs continue to run since VEXT is low. 8. PS_HOLD is low and VEXT goes high, RST pin goes low. 9. Delay between RST going low and LDO2 disabled. 10. Delay between LDO2 and LDO1 disabled. www.national.com 12 |
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